FM / checks

/opt/imh-python/lib/python3.9/site-packages/numpy/distutils/checks/

/opt/imh-python/lib/python3.9/site-packages/numpy/distutils/checks

Name	Size	Mode	Actions
cpu_asimd.c	818	0644	edit dl rm
cpu_asimddp.c	432	0644	edit dl rm
cpu_asimdfhm.c	529	0644	edit dl rm
cpu_asimdhp.c	379	0644	edit dl rm
cpu_avx.c	779	0644	edit dl rm
cpu_avx2.c	749	0644	edit dl rm
cpu_avx512cd.c	759	0644	edit dl rm
cpu_avx512f.c	755	0644	edit dl rm
cpu_avx512_clx.c	842	0644	edit dl rm
cpu_avx512_cnl.c	948	0644	edit dl rm
cpu_avx512_icl.c	1004	0644	edit dl rm
cpu_avx512_knl.c	956	0644	edit dl rm
cpu_avx512_knm.c	1132	0644	edit dl rm
cpu_avx512_skx.c	1010	0644	edit dl rm
cpu_avx512_spr.c	904	0644	edit dl rm
cpu_f16c.c	868	0644	edit dl rm
cpu_fma3.c	817	0644	edit dl rm
cpu_fma4.c	301	0644	edit dl rm
cpu_neon.c	600	0644	edit dl rm
cpu_neon_fp16.c	251	0644	edit dl rm
cpu_neon_vfpv4.c	609	0644	edit dl rm
cpu_popcnt.c	1049	0644	edit dl rm
cpu_sse.c	686	0644	edit dl rm
cpu_sse2.c	697	0644	edit dl rm
cpu_sse3.c	689	0644	edit dl rm
cpu_sse41.c	675	0644	edit dl rm
cpu_sse42.c	692	0644	edit dl rm
cpu_ssse3.c	705	0644	edit dl rm
cpu_vsx.c	478	0644	edit dl rm
cpu_vsx2.c	263	0644	edit dl rm
cpu_vsx3.c	250	0644	edit dl rm
cpu_vsx4.c	305	0644	edit dl rm
cpu_vx.c	461	0644	edit dl rm
cpu_vxe.c	788	0644	edit dl rm
cpu_vxe2.c	624	0644	edit dl rm
cpu_xop.c	234	0644	edit dl rm
extra_avx512bw_mask.c	636	0644	edit dl rm
extra_avx512dq_mask.c	504	0644	edit dl rm
extra_avx512f_reduce.c	1595	0644	edit dl rm
extra_vsx4_mma.c	499	0644	edit dl rm
extra_vsx_asm.c	945	0644	edit dl rm
test_flags.c	16	0644	edit dl rm

Edit: /opt/imh-python/lib/python3.9/site-packages/numpy/distutils/checks/cpu_avx512_skx.c (1010B)

#include <immintrin.h>

int main(int argc, char **argv)
{
    __m512i aa = _mm512_abs_epi32(_mm512_loadu_si512((const __m512i*)argv[argc-1]));
    /* VL */
    __m256i a = _mm256_abs_epi64(_mm512_extracti64x4_epi64(aa, 1));
    /* DQ */
    __m512i b = _mm512_broadcast_i32x8(a);
    /* BW */
    b = _mm512_abs_epi16(b);
    return _mm_cvtsi128_si32(_mm512_castsi512_si128(b));
}

#if defined(DETECT_FEATURES) && defined(__INTEL_COMPILER) /* * Unlike GCC and CLANG, Intel Compiler exposes all supported intrinsics, * whether or not the build options for those features are specified. * Therefore, we must test #definitions of CPU features when option native/host * is enabled via `--cpu-baseline` or through env var `CFLAGS` otherwise * the test will be broken and leads to enable all possible features. */ #if !defined(__AVX512VL__) || !defined(__AVX512BW__) || !defined(__AVX512DQ__) #error "HOST/ARCH doesn't support SkyLake AVX512 features" #endif #endif #include int main(int argc, char **argv) { __m512i aa = _mm512_abs_epi32(_mm512_loadu_si512((const __m512i*)argv[argc-1])); /* VL */ __m256i a = _mm256_abs_epi64(_mm512_extracti64x4_epi64(aa, 1)); /* DQ */ __m512i b = _mm512_broadcast_i32x8(a); /* BW */ b = _mm512_abs_epi16(b); return _mm_cvtsi128_si32(_mm512_castsi512_si128(b)); }