/opt/imh-python/lib/python3.9/site-packages/numpy/distutils/checks
NameSizeModeActions
cpu_asimd.c8180644editdlrm
cpu_asimddp.c4320644editdlrm
cpu_asimdfhm.c5290644editdlrm
cpu_asimdhp.c3790644editdlrm
cpu_avx.c7790644editdlrm
cpu_avx2.c7490644editdlrm
cpu_avx512cd.c7590644editdlrm
cpu_avx512f.c7550644editdlrm
cpu_avx512_clx.c8420644editdlrm
cpu_avx512_cnl.c9480644editdlrm
cpu_avx512_icl.c10040644editdlrm
cpu_avx512_knl.c9560644editdlrm
cpu_avx512_knm.c11320644editdlrm
cpu_avx512_skx.c10100644editdlrm
cpu_avx512_spr.c9040644editdlrm
cpu_f16c.c8680644editdlrm
cpu_fma3.c8170644editdlrm
cpu_fma4.c3010644editdlrm
cpu_neon.c6000644editdlrm
cpu_neon_fp16.c2510644editdlrm
cpu_neon_vfpv4.c6090644editdlrm
cpu_popcnt.c10490644editdlrm
cpu_sse.c6860644editdlrm
cpu_sse2.c6970644editdlrm
cpu_sse3.c6890644editdlrm
cpu_sse41.c6750644editdlrm
cpu_sse42.c6920644editdlrm
cpu_ssse3.c7050644editdlrm
cpu_vsx.c4780644editdlrm
cpu_vsx2.c2630644editdlrm
cpu_vsx3.c2500644editdlrm
cpu_vsx4.c3050644editdlrm
cpu_vx.c4610644editdlrm
cpu_vxe.c7880644editdlrm
cpu_vxe2.c6240644editdlrm
cpu_xop.c2340644editdlrm
extra_avx512bw_mask.c6360644editdlrm
extra_avx512dq_mask.c5040644editdlrm
extra_avx512f_reduce.c15950644editdlrm
extra_vsx4_mma.c4990644editdlrm
extra_vsx_asm.c9450644editdlrm
test_flags.c160644editdlrm
Edit: /opt/imh-python/lib/python3.9/site-packages/numpy/distutils/checks/extra_vsx_asm.c (945B)
/** * Testing ASM VSX register number fixer '%x' * * old versions of CLANG doesn't support %x in the inline asm template * which fixes register number when using any of the register constraints wa, wd, wf. * * xref: * - https://bugs.llvm.org/show_bug.cgi?id=31837 * - https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html */ #ifndef __VSX__ #error "VSX is not supported" #endif #include #if (defined(__GNUC__) && !defined(vec_xl)) || (defined(__clang__) && !defined(__IBMC__)) #define vsx_ld vec_vsx_ld #define vsx_st vec_vsx_st #else #define vsx_ld vec_xl #define vsx_st vec_xst #endif int main(void) { float z4[] = {0, 0, 0, 0}; signed int zout[] = {0, 0, 0, 0}; __vector float vz4 = vsx_ld(0, z4); __vector signed int asm_ret = vsx_ld(0, zout); __asm__ ("xvcvspsxws %x0,%x1" : "=wa" (vz4) : "wa" (asm_ret)); vsx_st(asm_ret, 0, zout); return zout[0]; }